`timescale 1ns/1ps
module test_bench
#(
	parameter SIZE_ADC_DATA                                     = 11;
	parameter SIZE_FILTER_DATA                                  = 15;)

	reg                                                 reset;
	reg                                                 clk;
//------------------------------------------------------------------------
	wire [SIZE_ADC_DATA:0]                              output_data;
//------------------------------------------------------------------------
    integer                                                      f;
    integer                                                      openF;
    reg [80:0]                                                  str;
//------------------------------------------------------------------------


	v7_filter FilterV7 (
		.clk                                                  (clk),
		.reset                                                (reset),
		.input_data                                           (output_data_exp_sig_gen),
		.output_data                                          (output_data_v7));



    initial begin
        f                                              = $fopen("input.txt","r");
        clk                                           <= 0;
        openF                                          = 1;
        reset                                         <= 0;
        #10 reset                                     <= 1;
    end

	always #4
	begin
		if (!reset)
		begin
			output_data <= 0;
		end
		else
		begin            
            if( openF )
            begin
                openF = $fgets(str, fd);
                $sscanf(str, "%f", output_data);
            end
            else
            begin
                $fclose(f);  
                $finish;
            end
            clk = ~clk;
		end        
	end    
endmodule

